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flash memory 1 k9f1208r0c k9f1208u0c K9F1208B0C k9f1208x0c * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
flash memory 2 k9f1208r0c k9f1208u0c K9F1208B0C document title 64m x 8 bits nand flash memory revision history the attached datasheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electr onics will evaluate and reply to your re quests and questions about device. if you h ave any questions, please contact the sam sung branch office near you. revision no. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 1.1 remark advance advance advance advance advance preliminary final final history initial issue. 2.7v part is added address of read 2 is changed (a 4 ~a 7 : don?t care -> fixed "low" ) 1. add trps/trcs/treas parameter for status read 2. add nwp timing guide 1. change from trps/trcs/treas to trpb/trcb/treab parameter for 1.8v device busy state 1. sequential row read is added 1. tcry is changed (50ns+tr(r/b) --> 5us) 1. mode selection is modified ("ce don?t care" case) draft date nov. 10th 2005 july 13th 2006 aug. 1st 2006 oct. 12th 2006 nov. 14th 2006 nov. 15th 2006 dec. 28th 2006 june 18th 2007 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.samsung.com/products/semiconductor/
flash memory 3 k9f1208r0c k9f1208u0c K9F1208B0C general description features ? voltage supply - 1.8v device(k9f1208r0c) : 1.65v ~ 1.95v - 2.7v device(K9F1208B0C) : 2.5v ~ 2.9v - 3.3v device(k9f1208u0c) : 2.7v ~ 3.6v ? organization - memory cell array : (64m + 2m) x 8bits - data register : (512 + 16) x 8bits ? automatic program and erase - page program : (512 + 16) x 8bits - block erase : (16k + 512)bytes ? page read operation - page size : (512 + 16)bytes - random access : 15 s(max.) - serial page access : 42ns(min.) ? fast write cycle time - program time : 200 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions 64m x 8 bits nand flash memory ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles ( with 1bit/512byte ecc) - data retention : 10 years ? command register operation ? unique id for copyright protection ? package - k9f1208u0c-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9f1208x0c-jcb0/jib0: pb-free package 63-ball fbga(8.5 x 13 x 1.2mmt) - K9F1208B0C-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) offered in 64mx8bits, the k9f1208x0c is 512mbit with spare 16mbit capacity. the device is offered in 1.8v, 2.7v and 3.3v vcc. i ts nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can be perform ed in typical 200 s on the 528-bytes and an erase operation can be performed in ty pical 2ms on a 16k-bytes block. data in the page can be read out at 42ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command i nput. the on-chip write control automates all program and erase functi ons including pulse repetition, where required, and internal ve rifica- tion and margining of data. even the write-intens ive systems can take advantage of the k9f1208x0c s extended reliability of 100k program/erase cycles by providing ecc(error correc ting code) with real time mapping-out algorithm. the k9f1208x0c is an optimum solution for large nonvolatile stor age applications such as solid state file storage and other por table applications requiring non-volatility. product list part number vcc range organization pkg type k9f1208r0c-j 1.65v ~ 1.95v x8 fbga K9F1208B0C-p 2.5v ~ 2.9v tsop1 k9f1208u0c-p 2.7v ~ 3.6v tsop1 k9f1208u0c-j fbga
flash memory 4 k9f1208r0c k9f1208u0c K9F1208B0C pin configuration (tsop1) k9f1208x0c-pcb0/pib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic th in small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03
flash memory 5 k9f1208r0c k9f1208u0c K9F1208B0C k9f1208x0c-jcb0/jib0 r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c pin configuration (fbga) 3456 1 2 a b c d g e f h top view
flash memory 6 k9f1208r0c k9f1208u0c K9F1208B0C 8.50 0.10 #a1 side view top view 63-ball fbga (measured in millimeters) 0.90 0.10 0.45 0.05 4321 a b c d g bottom view 13.00 0.10 63- ? 0.45 0.05 0.80 x 7= 5.60 13.00 0.10 0.80 x 5= 4.00 0.80 0.35 0.05 0.10max b a 2.80 2.00 8.50 0.10 (datum b) (datum a) 0.20 m a b ? 0.80 0.80 x 11= 8.80 0.80 x 9= 7.20 65 13.00 0.10 e f h #a1 index mark(optional)
flash memory 7 k9f1208r0c k9f1208u0c K9F1208B0C pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comma nds sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase opertion. regarding ce control during read operation, refer to ?page read? section of device operation . re read enable the re input is the serial data-out control, and when acti ve drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. comm ands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to hi gh state upon completion. it is an open drain output and does not float to high-z condition when the ch ip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected.
flash memory 8 k9f1208r0c k9f1208u0c K9F1208B0C 512bytes 16 bytes figure 1. k9f1208x0c functional block diagram figure 2. k9f1208x0c array organization v cc x-buffers 512m + 16m bits command nand flash array (512 + 16)bytes x 131,072 y-gating page register & s/a i/o buffers & latches y-buffers control logic global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 128k pages (=4,096 blocks) 512 bytes 8 bits 16 bytes 1 block = 32 pages = (16k + 512) bytes i/o 0 ~ i/o 7 1 page = 528 bytes 1 block = 528 bytes x 32 pages = (16k + 512) bytes 1 device = 528bytes x 32pages x 4,096 blocks = 528 mbits column address row address (page address) page register cle ale note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 *l *l *l *l *l *l *l register & high voltage generator latches & decoders latches & decoders
flash memory 9 k9f1208r0c k9f1208u0c K9F1208B0C product introduction the k9f1208x0c is a 528mbits(553,648,218 bits) memory organ ized as 131,072 rows(pages) by 528 columns. spare sixteen col- umns are located from column address of 512 to 527. a 528-bytes dat a register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. ea ch of the 16 cells resides in a different page. a block consis ts of the 32 pages formed two nand structures. a nand structure consists of 16 cells. total 135,168 nand structures reside in a block. t he program and read operations are executed on a page basis, whil e the erase operation is execut ed on a block basis. the memory array consists of 4,096 separately erasabl e 16k-bytes blocks. it indicates that the bit by bit erase operation is prohibited on the k9f1208x0c. the k9f1208x0c has addresses multiplexed into 8 i/o's. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. comm and, address and data are all written throu gh i/o's by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respec tively, via the i/o pins. the 64m byte physical space require s 26 addresses, thereby requiring four cycles fo r byte-level addressing : 1 cycle of colu mn address, 3 cycles of row address, in that order. page read and page program need the same four address cycl es following the required command input. in block erase oper- ation, however, only the 3 cycles of row address are used. device operations are select ed by writing specific commands into the command register. table 1 defines the specific commands of the k9f1208x0c. table 1. command sets note : 1. the 00h/01h command defines starting address of the 1st/2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half reg ister(00h) on the next cycle. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1?st cycle 2?nd cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h block protect 1 41h - block protect 2 42h - block protect 3 43h - read status 70h - o read protection status 7ah -
flash memory 10 k9f1208r0c k9f1208u0c K9F1208B0C dc and operating characteristics (recommended operating cond itions otherwise noted.) notes : 1. typical values are measured at vcc=3.3v, ta=25 c. and not 100% tested. parameter symbol test conditions k9f1208x0c uni t 1.8v 2.7v 3.3v min typ max min typ max min typ max operating current sequential read icc1 trc=42ns, ce =v il , i out =0ma - 8 20 - 10 20 - 10 20 ma program icc2 - - 8 20 - 10 20 - 10 20 erase icc3 - - 8 20 - 10 20 - 10 20 stand-by current(ttl) isb1 ce =v ih , wp =0v/v cc --1 - -1 --1 stand-by current(cmos) isb2 ce =v cc -0.2, wp =0v/v cc -1050 - 1050 -1050 a input leakage current i li v in =0 to vcc(max) -- 10 - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) -- 10 - - 10 - - 10 input high voltage v ih v cc -0.4 - v cc +0.3 v cc -0.4 - v cc +0.3 2.0 - v cc +0. 3 v input low voltage, all inputs v il - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8 output high voltage level v oh k9f1208r0c: i oh =-100 a K9F1208B0C: i oh =-100 a k9f1208u0c: i oh =-400 a v cc -0.1 -- v cc -0.4 --2.4-- output low voltage level v ol k9f1208r0c: i ol =100 a K9F1208B0C: i ol =100 a k9f1208u0c: i ol =2.1ma - - 0.1 - - 0.4 - - 0.4 output low current(r/b ) i ol (r/b )v ol =0.4v 34- 34- 810-ma recommended operating conditions (voltage reference to gnd at the condision of k9f1208x0c-xcb0 : t a =0 to 70 c or k9f1208x0c-xib0 : t a =-40 to 85 c) parameter symbol 1.8v(k9f1208r0c) 2.7v(K9F1208B0C) 3.3v(k9f1208u0c) unit min typ. max min typ. max min typ. max supply voltage v cc 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 v v ss 0000 0 0000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transit ions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit 1.8v device 2.7v/3.3v device voltage on any pin relative to vss v cc -0.6 to + 2.45 -0.6 to + 4.6 v v in -0.6 to + 2.45 -0.6 to + 4.6 v i/o -0.6 to vcc + 0.3 (< 2.45v) -0.6 to vcc + 0.3 (< 4.6v) temperature under bias k9f1208x0c-xcb0 t bias -10 to +125 c k9f1208x0c-xib0 -40 to +125 storage temperature k9f1208x0c-xcb0 t stg -65 to +150 c k9f1208x0c-xib0 short circuit current i os 5ma
flash memory 11 k9f1208r0c k9f1208u0c K9F1208B0C capacitance (ta=25 c, vcc=1.8v/2.7v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f1208x0c may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the nu mber of valid blocks is presented with both cases of invalid blocks considered. invali d blocks are defined as blocks that contain one or more bad bi ts. do not erase or program factory-marked bad blocks. refer to the attached techni cal notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guarant eed to be a valid block up to 1k program/erase cycles with 1 bit/512byte ecc. 3. minimum 1,004 valid blocks are guaranteed for each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 4,026 - 4,096 blocks ac test condition (k9f1208x0c-xcb0 :ta=0 to 70 c, k9f1208x0c-xib0:ta=-40 to 85 c). parameter value k9f1208r0c K9F1208B0C k9f1208u0c input pulse levels 0v to v cc 0v to vcc 0.4v to 2.4v input rise and fall times 5ns 5ns 5ns input and output timing levels v cc /2 vcc/2 1.5v k9f1208r0c:output load (vcc:1.8v +/-10%) K9F1208B0C:output load (vcc:2.7v +/-10%) k9f1208u0c:output load (vcc:3.3v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=30pf 1 ttl gate and cl=100pf k9f1208u0c:output load (vcc:3.0v +/-10%) - - 1 ttl gate and cl=50pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input (4 clocks) hll hh write mode command input l h l h h address input (4 clocks) l l l h h data input l l l h x data output l l l h h x during read (busy) on k9f1208x0c_p x x x x h x during read (busy) except on k9f1208x0c_p x x x x x h during program (busy) x x x x x h during erase (busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by
flash memory 12 k9f1208r0c k9f1208u0c K9F1208B0C program / erase characteristics note note: 1.typical program time is defined as the time within which more than 50% of the whole pages are programmed at vcc of 3.3v and 2 5?c parameter symbol min typ max unit program time t prog (1) - 200 500 s number of partial program cycles in the same page main array nop --1cycle spare array - - 2 cycle block erase time t bers -23ms ac timing characteristics for command / address / data input note : the transition of the corresponding control pins must occur only once while we is held low . parameter symbol min max unit cle setup time t cls 21 - ns cle hold time t clh 5-ns ce setup time t cs 31 - ns ce hold time t ch 5-ns we pulse width t wp (1) 21 - ns ale setup time t als 21 - ns ale hold time t alh 5-ns data setup time t ds 20 - ns data hold time t dh 5-ns write cycle time t wc 42 - ns we high hold time t wh 15 - ns
flash memory 13 k9f1208r0c k9f1208u0c K9F1208B0C ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. this parameter ( t rpb/ t rcb/ t reab) must be used only for 1.8v device. 3. the time to ready depends on the value of the pull-up resistor tied r/b pin. parameter symbol min max unit data transfer from cell to register t r -15 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 21 - ns we high to busy t wb -100ns read cycle time t rc 42 - ns re access time t rea -30ns ce access time t cea -35ns re high to output hi-z t rhz -30ns ce high to output hi-z t chz -20ns ce high to ale or cle don?t care t csd 10 - ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0-ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s re pulse width during busy state t rpb (2) 35 - ns read cycle time during busy state t rcb (2) 50 - ns re access time during busy state t reab (2) -40ns parameter symbol min max uni k9f1208x0c-p only last re high to busy(at sequential read) t rb -100ns ce high to ready(in case of interception by ce at read) t cry - 5 s ce high hold time(at the last serial read) (4) t ceh 100 - ns
flash memory 14 k9f1208r0c k9f1208u0c K9F1208B0C nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is so call ed as the initial invalid block information. devices with init ial invalid block(s) have the same quality level as devic es with all valid blocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) bec ause it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) vi a address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a vali d block up to 1k program/erase cycles with 1bit /512byte ecc. all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd pag e of every initial invalid block has non-ffh data at the column addre ss of 517. since the initial in valid block information is also erasable in most cases, it is impossible to recover the information onc e it has been erased. therefore, the system must be able to recog nize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug- gested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address 517 figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial invalid block(s) table of the 1st and 2nd page in the block
flash memory 15 k9f1208r0c k9f1208u0c K9F1208B0C nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, the additional invali d blocks may develop with nand flash memory . refer to the qualification report for t he block failure rate.the following possible failur e modes should be considered to implement a highly reliable system. in the case of st atus read failure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block repl acement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and c opying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read failure due to single bit error sh ould be reclaimed by ecc without any block repl acement. the block failure rate in the qual ification report does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read af ter erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bits detection : if program operation results in an error, map out the block including the page in error and copy the * target data to another block.
flash memory 16 k9f1208r0c k9f1208u0c K9F1208B0C erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1. when an error happens in the nth page of th e block ?a? during erase or program operation. * step2. copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3. then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4. do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { 1st (n-1)th nth (page) { an error occurs.
flash memory 17 k9f1208r0c k9f1208u0c K9F1208B0C samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command set s the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effe ctive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data st arting from ?a? or ?c? area, ?00h? or ?50h? command must be in putted before ?80h? command is written. a complete read operation prio r to ?80h? command is not necessary. to program data starting fr om ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~511), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9f1208x0c table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 bytes (00h plane) "b" area (01h plane) "c" area (50h plane) 256 bytes 16 bytes "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 4. block diagram of pointer operation
flash memory 18 k9f1208r0c k9f1208u0c K9F1208B0C system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. in additi on, for voice or audio applications which us e slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(4cycle) 00h ce cle ale we i/o x data output(sequential) ce don?t-care r/b t r re figure 5. program operation with ce don?t-care. figure 6. read operation with ce don?t-care. ce we t wp t ch t cs start add.(4cycle) 80h data input ce cle ale we i/o x data input ce don?t-care 10h t cea out t rea ce re i/o x on k9f1208x0c-p ce must be held low during tr
flash memory 19 k9f1208r0c k9f1208u0c K9F1208B0C * command latch cycle * address latch cycle ce we cle ale i/o x command t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale i/o x a0~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp a9~a16 a17~a24 a25~a26
flash memory 20 k9f1208r0c k9f1208u0c K9F1208B0C * input data latch cycle * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox t chz* t rhz* ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox
flash memory 21 k9f1208r0c k9f1208u0c K9F1208B0C status read cycle (during ready state) ce we cle re i/o x 70h/7ah status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls t chz t rhz t rp status read cycle (during busy state) ce we cle re i/o x 70h/7ah status output t clr t clh t cs t wp t ch t ds t dh t reab t ir t oh t oh t whr t cea t cls t chz t rhz t rpb r/b r/b
flash memory 22 k9f1208r0c k9f1208u0c K9F1208B0C t chz t oh read1 operation (read one page) x8 device : m = 528 , read cmd = 00h or 01h 1) notes : 1) is only valid on k9f1208x0c-p on k9f1208x0c-p ce must be held low during tr 1) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar t r t rc t rhz t rr dout m t rb t cry t wc a 25 t ceh 1) n address t oh on k9f1208u0c-p ce must be held low during tr read1 operation (intercepted by ce ) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc a 25 t oh
flash memory 23 k9f1208r0c k9f1208u0c K9F1208B0C on k9f1208x0c-p ce must be held low during tr read2 operation (read one page) ce cle r/b i/o x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n+m m address n+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care a 25 selected row start address m 512 16 sequential row read operation (within a block) ce cle r/b i/o x we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout 527 dout 0 dout 1 dout 527 busy m+1 output n ready a 25
flash memory 24 k9f1208r0c k9f1208u0c K9F1208B0C page program operation ce cle r/b i/o x we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc a 25 block erase operation (erase one block) ce cle r/b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc a 25
flash memory 25 k9f1208r0c k9f1208u0c K9F1208B0C read id operation ce cle i/o x we ale re 90h read id command maker code device code 00h ech 76h t rea address. 1cycle 5ah 3fh id defintition table 90 id : access command = 90h value description 1 st byte 2 nd byte 3 rd byte 4 th byte ech 76h 5ah 3fh maker code device code don?t support copy back operation don?t support multi plane operation
flash memory 26 k9f1208r0c k9f1208u0c K9F1208B0C device operation page read upon initial device power up, the device defaults to read1 mode. th is operation is also initiated by writing 00h to the command regis- ter along with four address cycles. once the command is latched, it does not need to be written for the following page read ope ration. three types of operations are available : r andom read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. t he 528 bytes of data within the selected page are transferre d to the data registers in less than 15 s(t r ). the system controller can detect the comple tion of this data transfer(tr) by analyzing the output of r/b pin. ce must be held low while in busy for k9f1208x0c-pxb0, while ce is don?t-care with k9f1208x0c-jxb0. if ce goes high before the device returns to ready, the random read oper ation is interrupted and busy returns to ready as the defined by tcry. since the operation was aborted, the serial page read does not output valid data. once the data in a page is loaded into the reg- isters, they may be read out in 42ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stat- ing from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 51 2 to 527 bytes may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. the read1 command(00h/01h) is needed to move the pointer back to the main area. fig- ures 7 to 10 show typical sequence and timings for each read operation. sequential row read is available only on k9f1208x0c-p : after the data of last column address is clocked out, the next page is automatically selected fo r sequential row read. waiting 15 s again allows reading the selected page. the sequentia l row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 oper ation is allowed only within a block and after the last p age of a block is readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 9, 10 show typical sequence and timings for sequential row read operation.
flash memory 27 k9f1208r0c k9f1208u0c K9F1208B0C figure 7. read1 operation start add.(4cycle) 00h data output(sequential) ce cle ale r/b we i/o 0 ~ 7 re t r a 0 ~ a 7 & a 9 ~ a 25 (00h command) data field spare field main array (01h command) data field spare field 1st half array 2st half array note : 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at nex t cycle. 1) on k9f1208x0c-p ce must be held low during tr
flash memory 28 k9f1208r0c k9f1208u0c K9F1208B0C figure 8. read2 operation 50h data output(sequential) spare field ce cle ale r/b we start add.(4cycle) i/o x re t r a 0 ~ a 3 & a 9 ~ a 25 main array data field spare field (a 4 ~ a 7 : fixed "low") on k9f1208x0c-p ce must be held low during tr
flash memory 29 k9f1208r0c k9f1208u0c K9F1208B0C figure 9. sequential row read1 operation (only for k9f1208x0c-p valid within a block) 00h 01h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/b start add.(4cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) t r t r t r the sequential read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation mu st be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. ( 00h command) data field spare field ( 01h command) data field spare field 1st half array 2nd half array 1st 2nd nth 1st half array 2nd half array 1st 2nd nth block figure 10. sequential row read2 operation (only for k9f1208x0c-p valid within a block) 50h a 0 ~ a 3 & a 9 ~ a 25 i/o x r/b start add.(4cycle) data output data output data output 2nd nth (16byte) (16byte) 1st t r t r t r data field spare field 1st block (a 4 ~ a 7 : don?t care) nth
flash memory 30 k9f1208r0c k9f1208u0c K9F1208B0C page program the device is programmed basically on a page ba sis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 byte, in a single page program cycle. the number of consecutive partial page programmi ng operation within the same pa ge without an intervening erase operation must not exceed 1 for main array and 2 for spare array. the addressing may be done in an y random order in a block. a page program cycle consists of a se rial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming per iod where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to the atta ched technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the four cycle address input and then serial data loading. the bytes other than those to be pr ogrammed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate th e pro- gramming process. the internal write state control automatically executes the algorithms and timi ngs necessary for program and verify, thereby freeing the system controll er for other tasks. once the program proc ess starts, the read status register comman d may be entered, with re and ce low, to read the status register. the system c ontroller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 11 ). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remai ns in read status command mode until another valid command is written to the command register. figure11. program operation 80h a 0 ~ a 7 & a 9 ~ a 25 i/o 0 ~ 7 r/b address & data input i/o 0 pass 528 bytes data 10h 70h fail t prog figure 12. block erase operation block erase the erase operation is done on a block(16k byte s) basis. block address loading is accomp lished in three cycles initiated by an erase setup command(60h). only address a 14 to a 26 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing proce ss. this two-step sequence of setup followed by execution command ensures that memory contents are not accident ally erased due to exte rnal noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bi t(i/o 0) may be checked. figure 8 details the sequence. 60h block add. : a 14 ~ a 25 i/o x r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers
flash memory 31 k9f1208r0c k9f1208u0c K9F1208B0C figure 13. block protect operation block protect each block is protected from programming and erasing, controlled by the protect flag wr itten in a specified area in the block. block proctect opreation is initiated by wirting 4xh-80h-10h to the command register along with four address cycles. only address a 14 to a 26 is valid while a 0 to a 13 is fixed as 00h. the data must not be loaded. on ce the block protect opreation starts, the read status register command may be entered, with re and ce low, to read the status register. the system controller can detect the completion of page program operation for protecting a block by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while block protec t operation is in progress. but, if reset command is inputted while block protect operation is in progre ss, the block will not be guaranteed whether it is protected or not. when the page pr ogram operation for protecting a block is completed, the write status bit(i/o 0) may be checked(figure 13). the command register rema ins in read status command mode until another valid command is written to the command register. when programming is prohibited by 41h command, the protect flag and the data of protec ted block can be erased by block erase operation. once erasing is prohibited by 42h/43h command, the pr otect flag and the data of protected block can not be erased. if 80h-10h is written to command register along with four address cycles at the program pr otected block or at the program/erase pr o- tected block, and if 60h-d0h is written to command register al ong with three address cycles at the program/erase protected bloc k, the r/b pin changes to low for tr. the block pr otect operation must not be excuted on the al eady protected block. the block protect operation will be aborted by reset command( ffh). the block protect operation can only be used from first block to 200th block. the device contains a status register wh ich may be used to read out the state of the selected block. after writing 7ah command to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , which- ever occurs last(figure 14). refer to table 3 for specific stat us register definitions. the command register remains in status read mode until further commands are issued to it. 80h a 0 ~ a 7 : 00h fix i/o x r/b address input(4cycle) i/o 0 pass 10h 70h fail t prog three commands are provided to protect the block. 41h : programming is prohibited 42h : erasing is prohibited 43h : both programming and erasing are prohibited ffh ffh 4xh a 9 ~ a 13 : 00h fix a 14 ~ a 25 : 0 to 4095
flash memory 32 k9f1208r0c k9f1208u0c K9F1208B0C table 3. status register definition for 7ah command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o status definition i/o 0 programming protect not protected : "0" protected : "1" i/o 1 erasing protect not protected : "0" protected : "1" i/o 2 not use don?t -cared i/o 3 not use don?t -cared i/o 4 not use don?t -cared i/o 5 not use don?t -cared i/o 6 device operation busy: "0" ready : "1" i/o 7 write protect protected : "0" not protect : "1" ale we cle i/o x 00h a 9 ~ a 16 a 0 ~ a 7 a 25 7ah status a0~7 : 00h, a9~13 : 0 fixed, a14~25 : 0 to 4095 a 17 ~ a 24 re r/b t r figure 14. read block status
flash memory 33 k9f1208r0c k9f1208u0c K9F1208B0C read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. af ter writing 70h command to the co mmand register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status register is read during a random read cycle, a read command(00h or 50h) shoul d be given before sequential page read cycle. table 4. status register definition for 70h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. . i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1" read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code( ech), and the device code and 3rd, 4th cycle id respectively. the command register remains in read id mode until further co mmands are issued to it. figure 15 shows the operation sequence. figure 15. read id operation ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code t cea t ar t rea 5ah 3fh t whr device device device code k9f1208r0c 36h K9F1208B0C 76h k9f1208u0c 76h code
flash memory 34 k9f1208r0c k9f1208u0c K9F1208B0C figure 16. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort thes e operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or eras ed. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 16 below. ffh i/o x r/b t rst table 5. device status after power-up after reset operation mode 00h command is latched waiting for next command
flash memory 35 k9f1208r0c k9f1208u0c K9F1208B0C ready/busy the device has a r/b output that provides a hardware method of indica ting the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obta ined with the following reference chart(fig 17). its value can be determined by the following guidance. r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol v ol : 0.4v, v oh : 2.4v c l 1.8v device - v ol : 0.1v, v oh : vcc-0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v v cc 2.7v device - v ol : 0.4v, v oh : vcc q -0.4v
flash memory 36 k9f1208r0c k9f1208u0c K9F1208B0C tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 100pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 rp(min, 2.7v part) = v cc (max.) - v ol (max.) i ol + i l = 2.5v 3ma + i l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.7v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55 figure 17. rp vs tr ,tf & rp vs ibusy
flash memory 37 k9f1208r0c k9f1208u0c K9F1208B0C the device is designed to offer protection from any involuntary program/erase during pow er-transitions. an internal voltage de tector disables all functions when ever vcc is below about 1.1v(1.8v device) , 1.8v(2.7v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before internal circuit gets ready for any command seq uences as shown in figure 18. the two step command sequence for program/erase provides additional software protection. data protection & power-up sequence figure 18. ac waveforms for power transition v cc wp high we 3.3v device : ~ 2.5v 3.3v device : ~ 2.5v 100 s 2.7v device : ~ 2.0v 2.7v device : ~ 2.0v 1.8v device : ~ 1.5v 1.8v device : ~ 1.5v
flash memory 38 k9f1208r0c k9f1208u0c K9F1208B0C wp ac timing guide enabling wp during erase and program busy is prohibited. the eras e and program operations are enabled and disabled as follows: figure a-1. program operation 1. enable mode 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode 80h 10h tww(min.100ns) 1. enable mode 60h d0h tww(min.100ns) 2. disable mode 60h d0h tww(min.100ns) figure a-2. erase operation we i/o wp r/b we i/o wp r/b we i/o wp r/b

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